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The importance of bond strength measurement
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Written by Bob Sykes   
Saturday, 21 August 2010

Electrical and thermal bonds are such an integral part of electronic and semiconductor construction that they may often be taken for granted. Modern electronic assembly methods employ a myriad of bonding processes, each one a vital step in the manufacture of the final product.

 
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
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Written by Rex Anderson, Tong Yan Tee, Long Bin Tan et al   
Saturday, 21 August 2010

The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.

 
Drag soldering: how, when & why
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Written by Bob Doetzer   
Saturday, 03 July 2010

There is no doubt about it: automated machine processes are the most efficient methods for electronics assembly. That does not mean that there are not still occasions when hand soldering of individual components or assemblies is necessary.

 
Zoom fixture technology for ATE testing
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Written by Gary F. St.Onge   
Saturday, 03 July 2010

This paper details a breakthrough technology for automatic test equipment (ATE) fixtures. These new fixtures address the current market needs for faster delivery times, lower cost and access to finer pitch and smaller test targets.

 
PCB assembly system set-up for package-on-package (PoP) assembly
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Written by Gerry Padnos   
Monday, 14 June 2010

Traditional SMT assembly is a two dimensional process. Each component is placed on the same horizontal plane in different X and Y locations. In package on package (PoP) assembly, components are placed on successively higher layers. Since components are stacked on top of each other, traditional solder paste printing cannot be used.

 
New opportunities for controlling pressure in flip chip assembly
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Written by George A. Riley, PhD   
Monday, 14 June 2010

Pressure indicating film can immediately produce an image of pressure variations across an entire surface area, allowing significant differences in bond pressure across wafer bonder surfaces to be identified and corrected.

 
ESD Damage Models and Chemical Kinetics Part II (Charge induced and Field induced models)
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Written by C. S. Sudheendranath, ESD Management & Consultancy Pvt. Ltd., Bangalore   
Monday, 07 June 2010

In order to control and minimize damage caused to sensitive electronic devices, the Industry has come up with four important models of damage: The Human Body Model, The Charged Device Model, The Field Induced Model and the Machine Model.

 
Advances in WLCSP technologies for growing market needs
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Written by R. Anderson, R. Chilukuri, T.Y. Tee, et al   
Monday, 31 May 2010

This paper will share current results of Amkor’s WLCSP board level reliability testing for both larger package size and smaller pitch.

 
Head-in-pillow: Identifying and highlighting suspect solder joints
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Written by Dr. Evstatin Krastev and Dr. David Bernard   
Monday, 31 May 2010

Head-in-pillow (HIP) or head-on-pillow (HOP) is the phenomena that can occur when incomplete wetting of a solder joint occurs after solder paste coalesces around, or near to, a ball grid array (BGA) solder ball after reflow but does not inter-mix, resulting in an open joint.

 
BGA assembly reliability—PWB quality is the key
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Written by Tom Clifford   
Friday, 30 April 2010

The quality of the circuit board‘s pad is a critical factor in the reliability of the solder joint attaching the BGA.

 
Metallization options for optimum chip-on-board assembly
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Written by Mukul Luthra   
Friday, 30 April 2010

When COB is merged within mainstream SMT, the choice of metallization has to serve both the SMT process and bonding—that choice can be a make or break factor.

 
ESD Damage Models and Chemical Kinetics Part I (HBM Discharge)
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Written by C. S. Sudheendranath, ESD Management & Consultancy Pvt. Ltd., Bangalore   
Tuesday, 13 April 2010

Ever since the Human Body Model was suggested in order to explain the cause of mining disasters, the fact that electrostatic discharges can cause serious problems of safety has been recognized.

 
Process challenges and solutions for embedding chip-on-board into mainstream SMT assembly
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Written by Mukul Luthra   
Monday, 01 March 2010

Merging COB into mainstream surface mount processes significantly improves footprint efficiency and cuts cost and lead-time.

 
Guidelines for establishing a lead-free wave soldering process for high-reliability
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Written by J. Scott Nelson, Harris Corporation, Palm Bay, FL, USA   
Monday, 01 March 2010

The use of lead-free alloys in commercial electronics has been underway for almost a decade, but the use of lead-free solder in high-reliability applications is still very limited.

 
Combating counterfeit components-industry initiatives for a global problem
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Written by Nigel Burtt   
Friday, 29 January 2010

The UK Electronics Alliance (UKEA) organised a seminar in a hotel near London Heathrow airport in October 2009 to discuss the problems the global electronics industry faces with component counterfeiting.

 
Investigation & development of tin-lead and lead-free solder pastes to reduce head-in-pillow defects
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Written by Jasbir Bath, Roberto Garcia,Noriyoshi Uchida, Hajime Takahashi, Gordon Clark and Manabu Itoh   
Friday, 29 January 2010

Over the last few years, there has been an increase in the rate of head-in-pillow component soldering defects across a broad segment of industries, including consumer, telecom and military.

 
The Agony and Ecstasy of Indian Electronics
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Written by Rajoo Goel, Secretary General, ELCINA   
Monday, 30 November 2009

The Ecstasy of Indian Electronics is the galloping market for its products while its Agony is the exasperatingly slow pace of growth in Electronics Manufacturing.

 
Reducing copper dissolution in lead-free assembly
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Written by D. Di Maio, C. P. Hunt and B. Willis   
Monday, 23 November 2009

During a successful soldering operation to a copper surface, a small amount of copper is dissolved to form a reliable interconnection and is perfectly normal.

 
Collaborative cleaning process innovations from managing experience and learning curves
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Written by Mike Bixenman, DBA and Dirk Ellis, Kyzen Corporation, and John Neiderman, Speedline Technologies   
Monday, 23 November 2009

Moore’s Law infers that the number of transistors on a chip doubles approximately every two years. Consistent with Moore’s Law, high reliability electronic devices build faster processing speed and memory capacity using increasing smaller platforms.

 
IMEC’s unique micronail chip makes electronics and bio cells communicate
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Written by Debasish Choudhury   
Monday, 16 November 2009

IMEC presents a unique microchip with microscopic nail structures that enable close communication between the electronics and biological cells.

 
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