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Basic printed board repair and rework for copper tracks and pads, part 2
Written by Debasish Choudhury   
Saturday, 21 August 2010

Last month we covered the process of parallel gap welding, materials, specifications, the repair sequence and quality and inspection. Here we finish up with step-by-step instructions for three methods of repairing and replacing copper pads.

 
The importance of bond strength measurement
Written by Bob Sykes   
Saturday, 21 August 2010

Electrical and thermal bonds are such an integral part of electronic and semiconductor construction that they may often be taken for granted. Modern electronic assembly methods employ a myriad of bonding processes, each one a vital step in the manufacture of the final product.

 
Integrated testing, modeling and failure analysis of CSPnl for board level reliability
Written by Rex Anderson, Tong Yan Tee, Long Bin Tan et al   
Saturday, 21 August 2010

The wafer level chip scale package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of certain electronic products, especially handheld devices like cell phones.

 
Basic printed board repair and rework for copper tracks and pads, part 1
Written by Bob Willis   
Saturday, 03 July 2010

With the ever expanding electronics industry and the further integration of designs comes the reduction in size. Tracks and gaps become smaller, consequently increasing possibility for breaks to occur within the circuit.

 
Drag soldering: how, when & why
Written by Bob Doetzer   
Saturday, 03 July 2010

There is no doubt about it: automated machine processes are the most efficient methods for electronics assembly. That does not mean that there are not still occasions when hand soldering of individual components or assemblies is necessary.

 
Zoom fixture technology for ATE testing
Written by Gary F. St.Onge   
Saturday, 03 July 2010

This paper details a breakthrough technology for automatic test equipment (ATE) fixtures. These new fixtures address the current market needs for faster delivery times, lower cost and access to finer pitch and smaller test targets.

 
Package on package (PoP) defects
Written by Bob Willis   
Monday, 14 June 2010

Package on package (PoP) assembly is new to many engineers. PoP introduces different processes, materials and challenges, which will undoubtedly highlight some process defects.

 
PCB assembly system set-up for package-on-package (PoP) assembly
Written by Gerry Padnos   
Monday, 14 June 2010

Traditional SMT assembly is a two dimensional process. Each component is placed on the same horizontal plane in different X and Y locations. In package on package (PoP) assembly, components are placed on successively higher layers. Since components are stacked on top of each other, traditional solder paste printing cannot be used.

 
New opportunities for controlling pressure in flip chip assembly
Written by George A. Riley, PhD   
Monday, 14 June 2010

Pressure indicating film can immediately produce an image of pressure variations across an entire surface area, allowing significant differences in bond pressure across wafer bonder surfaces to be identified and corrected.

 
ESD Damage Models and Chemical Kinetics Part II (Charge induced and Field induced models)
Written by C. S. Sudheendranath, ESD Management & Consultancy Pvt. Ltd., Bangalore   
Monday, 07 June 2010

In order to control and minimize damage caused to sensitive electronic devices, the Industry has come up with four important models of damage: The Human Body Model, The Charged Device Model, The Field Induced Model and the Machine Model.

 
Advances in WLCSP technologies for growing market needs
Written by R. Anderson, R. Chilukuri, T.Y. Tee, et al   
Monday, 31 May 2010

This paper will share current results of Amkor’s WLCSP board level reliability testing for both larger package size and smaller pitch.

 
Head-in-pillow: Identifying and highlighting suspect solder joints
Written by Dr. Evstatin Krastev and Dr. David Bernard   
Monday, 31 May 2010

Head-in-pillow (HIP) or head-on-pillow (HOP) is the phenomena that can occur when incomplete wetting of a solder joint occurs after solder paste coalesces around, or near to, a ball grid array (BGA) solder ball after reflow but does not inter-mix, resulting in an open joint.

 
Online training & education - the alternative way
Written by Bob Willis   
Saturday, 22 May 2010

Continued education is something everyone needs, but what are the alternatives to successfully disseminating experience and technical information in a cost effective manner?

 
Stencil cleaning options and board wash-offs
Written by Bob Willis   
Friday, 30 April 2010

Inevitably all stencils need to be cleaned to remove solder paste residues from the surface of the foil and from the apertures to prevent it drying and giving missed/incomplete prints.

 
BGA assembly reliability—PWB quality is the key
Written by Tom Clifford   
Friday, 30 April 2010

The quality of the circuit board‘s pad is a critical factor in the reliability of the solder joint attaching the BGA.

 
Metallization options for optimum chip-on-board assembly
Written by Mukul Luthra   
Friday, 30 April 2010

When COB is merged within mainstream SMT, the choice of metallization has to serve both the SMT process and bonding—that choice can be a make or break factor.

 
ESD Damage Models and Chemical Kinetics Part I (HBM Discharge)
Written by C. S. Sudheendranath, ESD Management & Consultancy Pvt. Ltd., Bangalore   
Tuesday, 13 April 2010

Ever since the Human Body Model was suggested in order to explain the cause of mining disasters, the fact that electrostatic discharges can cause serious problems of safety has been recognized.

 
Process challenges and solutions for embedding chip-on-board into mainstream SMT assembly
Written by Mukul Luthra   
Monday, 01 March 2010

Merging COB into mainstream surface mount processes significantly improves footprint efficiency and cuts cost and lead-time.

 
Synergy, the Occam process and twisted wire interconnect
Written by Joe Fjelstad   
Monday, 01 March 2010

Synergy is broadly defined as the additive benefit that is garnered when two or more seemingly unrelated elements are joined, combined or brought together in some manner.

 
Stencil cleaning options and board wash-offs
Written by Bob Wills   
Monday, 01 March 2010

Inevitably all stencils need to be cleaned to remove solder paste residues from the surface of the foil and from the apertures to prevent it drying and giving missed/incomplete prints.

 
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